Apparatus for multiplexing signals through I/O pins

ABSTRACT

One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signal line outside of the semiconductor chip. A transmitting circuit is configured to selectively multiplex the plurality of signal lines onto the I/O pin. A receiving circuit is configured to receive multiplexed data from the I/O pin, and to reverse the multiplexing so that values originally from the multiplexed signal lines are separated into distinct signals in the receiving circuit. Note that the transmitting circuit and the receiving circuit are driven by a common clock signal. The apparatus additionally includes an initialization circuit that selectively configures the transmitting circuit and the receiving circuit to multiplex at least one of the plurality of signal lines through the I/O pin.

RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.09/327,284, filed Jun. 7, 1999 now U.S. Pat. No. 6,697,387. Thisapplication hereby claims priority under 35 U.S.C §120 to U.S. patentapplication Ser. No. 09/327,284. The subject matter of this applicationis also related to the subject matter in U.S. patent application Ser.No. 09/327,291, filed Jun. 7, 1999 now U.S. Pat. No. 6,678,287.

BACKGROUND

1. Field of the Invention

The present invention relates to digital circuitry within a computersystem. More specifically, the present invention relates to a system formultiplexing multiple signal lines through an I/O pin on a semiconductorchip.

2. Related Art

Much of the interconnection circuitry in a microprocessor-based computersystem is typically aggregated in a “core logic” unit that couples themicroprocessor to other parts of the computer system, such as a memory,a peripheral bus and a graphics controller.

Providing such interconnection capability can require a large number ofI/O pins to accommodate all of the signal lines. Some computer systemsdeal with this I/O pin problem by partitioning interconnection circuitryacross multiple chips. For example, a typical personal computer systemincludes a north bridge chip, a south bridge chip, a super I/O chip andan I/O APIC chip to support interconnections between the microprocessorand other components within the computer system. Using multiple chips isexpensive because the multiple chips must be integrated together withina circuit board. This leads to additional expense in manufacturingcircuit boards and maintaining inventories of each type of chip.

It is preferable to integrate all of the interconnection circuitry in acomputer system into a single semiconductor chip. However, I/O pinlimitations on a single chip can present problems. For example, a singlecore logic chip that includes all of a computer system's interconnectioncircuitry requires interfaces for a processor bus, a memory bus, an AGPbus for a graphics controller and a PCI bus for peripheral devices.Providing I/O pins for all of these interfaces requires many hundreds ofI/O pins, especially if any of the busses support 64 bit transfers. ThisI/O pin requirement can easily exceed the I/O pin limitations of asingle semiconductor chip.

It is desirable to somehow compress the signal lines feeding into a corelogic chip so that they flow through a smaller number of I/O pins. Onemethod of accomplishing this is to multiplex signal lines by usingadditional multiplexer select signals. For example, three extra selectlines can be used to multiplex eight signal lines through a single I/Opin. However, these extra select signals require additional I/O pins,which somewhat defeats the purpose of the multiplexing in the firstplace.

What is needed is a system that multiplexes multiple signal linesthrough a single I/O pin without using additional I/O pins for selectsignals.

SUMMARY

One embodiment of the present invention provides an apparatus thatselectively multiplexes a plurality of signal lines through an I/O pinon a semiconductor chip. This apparatus includes an I/O pin, forcoupling a signal line within the semiconductor chip to a signal lineoutside of the semiconductor chip. A transmitting circuit is configuredto selectively multiplex the plurality of signal lines onto the I/O pin.A receiving circuit is configured to receive multiplexed data from theI/O pin, and to reverse the multiplexing so that values originally fromthe multiplexed signal lines are separated into distinct signals in thereceiving circuit. Note that the transmitting circuit and the receivingcircuit are driven by a common clock signal. The apparatus additionallyincludes an initialization circuit that selectively configures thetransmitting circuit and the receiving circuit to multiplex at least oneof the plurality of signal lines through the I/O pin.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 illustrates a core logic unit with multiplexed I/O pins inaccordance with an embodiment of the present invention.

FIG. 2 illustrates a transmitting circuit coupled to a receiving circuitthrough an I/O pin in accordance with an embodiment of the presentinvention.

FIG. 3 illustrates a transmitting circuit coupled to a receiving circuitthrough an I/O pin in accordance with another embodiment of the presentinvention.

FIG. 4 illustrates the internal structure of an initialization circuitfor initializing the transmitting circuit and the receiving circuit inaccordance with an embodiment of the present invention.

FIG. 5 illustrates the internal structure of a control circuit forcontrolling an initialization circuit or a receiving circuit inaccordance with an embodiment of the present invention.

FIG. 6 is a flow chart illustrating operation of a transmitting circuitand a receiving circuit in accordance with an embodiment of the presentinvention.

FIG. 7 is a flow chart illustrating the operation of an initializationcircuit in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

The following description is presented to enable any person skilled inthe art to make and use the invention, and is provided in the context ofa particular application and its requirements. Various modifications tothe disclosed embodiments will be readily apparent to those skilled inthe art, and the general principles defined herein may be applied toother embodiments and applications without departing from the spirit andscope of the present invention. Thus, the present invention is notintended to be limited to the embodiments shown, but is to be accordedthe widest scope consistent with the principles and features disclosedherein.

Core Logic Unit

FIG. 1 illustrates core logic unit 102 including multiplexed I/O pins inaccordance with an embodiment of the present invention. The computersystem illustrated in FIG. 1 includes processors 112, 114 and 116, whichare coupled to processor bus 108. Processor 112, 114 and 116 may be anytype of general or special purpose processors, including, but notlimited to microprocessors, mainframe computers, digital signalprocessors, graphics processors and device controllers. Processor bus108 may be any type of communication channel for coupling a processor toother devices in a computer system, including peripheral devices, memorydevices and other processors.

Core logic unit 102 couples processor bus 108 to semiconductor memory104, graphics unit 110, and peripheral bus 106. As illustrated in FIG.1, core logic unit 102 contains processor interface 126 forcommunicating with processor bus 108, accelerated graphics port (AGP)128 for communicating with graphics unit 110, memory interface 122 forcommunicating with semiconductor memory 104, and bus interface 130 forcommunicating with peripheral bus 106. Interfaces 126, 128, 122 and 130are coupled together through switch 124, which can be any type ofswitching circuitry that is able to selectively couple together tointerfaces 126, 128, 122 and 130.

Semiconductor memory 104 can include any type of semiconductor memoryfor storing code and/or data for execution by processors 112, 114 and116.

Graphics unit 110 can include any special-purpose circuitry forperforming graphics operations, thereby allowing graphics computationsto be off-loaded from processors 112, 114 and 116.

Peripheral bus 106 may include any type of communication channel forcoupling core logic unit 102 to other devices in a computer system,including peripheral devices and memory devices. In one embodiment ofthe present invention, peripheral bus 106 is a PCI bus.

Transmitting Circuit and Receiving Circuit

FIG. 2 illustrates transmitting circuit 226 coupled to receiving circuit224 through I/O pin 214 in accordance with an embodiment of the presentinvention. Transmitting circuit 226 is located to the left of I/O pin214 in FIG. 2. It includes multiplexer (MUX) 204, MUX 210, controlcircuit 206 and initialization circuit 208. MUX 204 selects between anumber of inputs including signal_1 201, signal_2 202 and signal_N 203.One of these inputs is selected by select signal 205 from controlcircuit 206. This selected input becomes the output of MUX 204 whichfeeds into an input of MUX 210. MUX 210 takes an additional input(initialization data signal 207) and a select signal (initializationselect 209) from initialization circuit 208. The output of MUX 210 feedsinto I/O pin 214.

Receiving circuit 224 is generally to the right of I/O pin 214 in FIG.2. Receiving circuit 224 includes control circuit 216 and flip-flops(FFs) 218, 220 and 222. Control circuit 216 selectively enables FFs 218,220 and 222 to store signals 201, 202 and 203, respectively, therebyreversing the multiplexing process.

The circuit illustrated in FIG. 2 operates generally as follows. Duringan initialization phase, initialization circuit 208 loads initializationdata signal 207 into control circuit 206 within transmitting circuit226. Initialization circuit 208 additionally activates initializationselect signal 209 to load initialization data through I/O pin 214 intocontrol circuit 216 within receiving circuit 224. Initialization datasignal 207 includes configuration information specifying which of thesignals coupled to transmitting circuit 226 are to be multiplexedthrough I/O pin 214 into receiving circuit 224. Note that controlcircuits 206 and 216, as well as initialization circuit 208, areinitially synchronized by an assertion of reset signal 212.

During operation, on the transmitting side control circuit 206 activatesMUX 204 to selectively channel signals 201, 202 and 203 through I/O pin214. On the receiving side, control circuit 216 selectively enables FFs218, 220 and 222 to receive signals 201, 202 and 203, respectively, toreverse the multiplexing process. Note that control circuits 206 and 216are driven by a common clock signal 213.

In one embodiment of the present invention, the transmitting circuit 226is contained within a semiconductor chip (see dashed lines), while thereceiving circuit 224 is located outside of the semiconductor chip. Inanother embodiment, receiving circuit 224 is located within asemiconductor chip (see dashed lines), while the transmitting circuit226 is outside of the semiconductor chip. In yet another embodiment,transmitting circuit 226 is located within a first semiconductor chipand receiving circuit 224 is located within a second semiconductor chip.

Alternative Embodiment

FIG. 3 illustrates transmitting circuit 326 coupled to receiving circuit324 in accordance with another embodiment of the present invention. Thisembodiment is the same as the embodiment illustrated in FIG. 2 exceptthat transmitting circuit 326 is located on a first semiconductor chipincluding I/O pin 310 (see dashed line), and receiving circuit 324 islocated on a second semiconductor chip including I/O pin 314 (see dashedlines). Furthermore, initialization circuit 308 is located externallythe first and second semiconductor chips. Initialization data frominitialization circuit 308 feeds into control circuit 316 in receivingcircuit 324 in the same manner that it does in the embodimentillustrated in FIG. 2. However, initialization data feeds through I/Opin 310 in the reverse direction into control circuit 306 withintransmitting circuit 326. Note that control circuit 306 includes abi-directional enable signal 307 that feeds into bi-directional driversfor I/O pin 310. During the initialization process, bi-directionalenable signal 307 reverses the direction of the drivers so that data canbe loaded from initialization circuit 308 into control circuit 306.Otherwise, the circuitry in FIG. 3 operates in substantially the samemanner as the circuitry illustrated in FIG. 2.

Initialization Circuit

FIG. 4 illustrates the internal structure of initialization circuit 208for initializing transmitting circuit 226 and receiving circuit 224 inaccordance with an embodiment of the present invention. Initializationcircuit 208 receives reset signal 212 as an input and outputsinitialization data signal 207, as well as initialization select signal209. Bits 0 through n−1 from configuration register 402 are ANDed withbits 2 through n+1 of shift register 404. These ANDed signals are ORedtogether along with bits 0-1 of shift register 404 to createinitialization data signal 207, which feeds configuration informationinto transmitting circuit 226 and receiving circuit 224 (in FIG. 2).

Signals 2 through n+1 from shift register 404 are additionally ORedtogether (in OR gate 414) to produce initialization select signal 209,which feeds into the control input of MUX 210 in FIG. 2.

Upon reset, shift register 404 is initialized to all zero values exceptfor bit 0, which starts with a one value. During the initializationprocess, this one value shifts to ascending bit positions until iteventually shifts off the end of the shift register 404. Note that shiftregister 404 is two bits wider than configuration register 402. Thisprovides two bits (or two clock cycles) to move the circuit away fromthe reset event, so that any asynchronous problems related to the resetevent will be eliminated. Note that data from configuration register 402will not feed through OR gate 412 until the one value in shift register404 shifts from position 0 to position 2. Similarly, initializationselect signal 209 will not be active until after two clock cycles,because the one value must shift twice from position 0 to position 2before initialization select signal 209 is asserted. Hence, asinitialization circuit 208 operates, the contents of configurationregister 402 appears at the output of OR gate 412 as initialization datasignal 207.

Control Circuit

FIG. 5 illustrates the internal structure of control circuit 306 forcontrolling an initialization circuit or a receiving circuit inaccordance with an embodiment of the present invention. Control circuit306 receives inputs from initialization circuit 308 and reset signal212. It outputs select signal 305, which is used to control MUX 304 (seeFIG. 3).

Signal from initialization circuit 308 feeds through OR gate 502 into FF504. The output of FF 504 feeds into an additional input of OR gate 502.This circuit is used to detect the two-cycle synchronization pulse thatsignals the start of the initialization sequence. Signal frominitialization circuit 308 also feeds directly into control register 506in order to load control register 506. Reset signal 212 feeds into bothcontrol register 506 and FFs 504, 510 and 516.

Each bit of control register 506 indicates whether or not acorresponding signal is sampled. If all bits in control register 506have one values, all signals are sampled. When the most significant bitof control register 506 is loaded, this indicates to the system that theinitialization phase is complete, and the system switches into afunctional mode. One output from control register 506 feeds from theright-hand-side of control register 506, through FF 510 to becomebi-directional enable signal 307. Another output feeds into next selectunit 508. Next select unit 508 generates select signals that correspondto bits that are set in control register 506. These select signals aregenerated in rotating order. The output of next select unit 508 feedsthrough MUX 514 and FF 516 before becoming select signal 305. Note thatFF 516 may include a plurality of flip flops, one for each select line,instead of the single flip flop as is illustrated in FIG. 5.

Select load data 513 and zeros feed into MUX 512. The output of MUX 512feeds into an input of MUX 514. Select load data 513 is a bit patternrepresenting the first signal to sample. This pattern corresponds to theleast significant bit that is set in control register 506.

MUXs 512 and 514 working together generate select signal 305. Ifbi-directional enable signal 307 is about to be set, MUXs 512 and 514output select load data 513. If bi-directional enable signal 307 is notabout to be set, MUXs 512 and 514 output all zeros. Otherwise, MUXs 512and 514 output the select signals specified by control register 506 inrotating order.

Operation of Transmitting Circuit and Receiving Circuit

FIG. 6 is a flow chart illustrating operation of a transmitting circuitand a receiving circuit in accordance with an embodiment of the presentinvention. The system starts by synchronizing transmitting circuit 226and receiving circuit 224 (step 602). This may happen when reset signal212 is asserted. Next, the system initializes transmitting circuit 226and receiving circuit 224 with configuration information specifyingwhich signal lines are to be multiplexed through I/O pin 214 (step 604).After the initialization process is complete, the system multiplexesselected signal lines from transmitting circuit 226 through I/O pin 214into receiving circuit 224 (step 606). Note that transmitting circuit226 and receiving circuit 224 are driven by a common clock signal sothat they continue to stay synchronized with each other.

Operation of Initialization Circuit

FIG. 7 is a flow chart illustrating the operation of initializationcircuit 208 in accordance with an embodiment of the present invention.Initialization circuit 208 first receives reset signal 212 (step 702).Reset signal 212 sets all bits in control register 506 to zero valuesexcept for bit 0, which is set to a one value (step 704). Initializationcircuit 208 next waits two clock cycles to eliminate any potentialasynchronous problems arising from assertion of reset signal 212 (step706). Finally, initialization circuit 208 loads configurationinformation into transmitting circuit 226 and receiving circuit 224during subsequent clock cycles (step 708).

The foregoing descriptions of embodiments of the invention have beenpresented for purposes of illustration and description only. They arenot intended to be exhaustive or to limit the invention to the formsdisclosed. Accordingly, many modifications and variations will beapparent to practitioners skilled in the art. Additionally, the abovedisclosure is not intended to limit the invention. The scope of theinvention is defined by the appended claims.

1. An electronic device comprising: a semiconductor chip; an I/O pin onthe semiconductor chip, for transmitting signals to a signal lineoutside of the semiconductor chip; a transmitting circuit that isconfigured to selectively multiplex the plurality of signal lines ontothe I/O pin; and an initialization circuit, coupled to the transmittingcircuit that selectively configures the transmitting circuit tomultiplex at least one of the plurality of signal lines according toselection information and to transmit the selection information throughthe I/O pin, which is also used for subsequent data transmission.
 2. Thedevice of claim 1, further comprising a receiving circuit that isconfigured to receive multiplexed data from the I/O pin, and to reversethe multiplexing so that values originally from the multiplexed signallines are separated into distinct signals in the receiving circuit. 3.The device of claim 2, wherein the transmitting circuit and thereceiving circuit are driven by a common clock signal coupled to boththe transmitting circuit and the receiving circuit.
 4. The device ofclaim 2, further comprising a synchronizing circuit, coupled to thetransmitting circuit, the synchronizing circuit sending a reset signalto the transmitting circuit, the transmitting circuit operable totransmit the selection information from the I/O pin upon receiving thereset signal and to subsequently send output signals from the I/O pin,the output signals multiplexed according to the selection information.5. The device of claim 4, wherein the receiving circuit is coupled tothe synchronizing circuit and operable to receive the reset signal, thereceiving circuit receiving the selection information followingreceiving the reset signal and subsequently de-multiplexing themultiplexed signals according to the selection information.
 6. Thedevice of claim 4, wherein the initialization information is a signalline identifier.
 7. The device of claim 2, wherein the transmittingcircuit is located on the semiconductor chip and the receiving circuitis located off of the semiconductor chip.
 8. The device of claim 2,wherein the receiving circuit is located on the semiconductor chip andthe transmitting circuit is located off of the semiconductor chip. 9.The device of claim 1, wherein the semiconductor chip is a core logicchip that couples together a processor, a memory, and a peripheral busin a computer system.
 10. The device of claim 1, wherein theinitialization circuit is located externally to the semiconductor chip.11. The device of claim 1, wherein the initialization circuit isconfigured to initialize the transmitting circuit during a computersystem boot up operation.
 12. The device of claim 1, wherein thetransmitting circuit includes: a multiplexer for multiplexing theplurality of signal lines onto the I/O pin; and a control circuit thatcontrols the multiplexer so that the at least one of the plurality ofsignal lines is multiplexed onto the I/O pin.
 13. An electronic devicecomprising: an I/O pin; and a semiconductor chip coupled to the I/O pinand comprising a receiving circuit that is configured to selectivelyde-multiplex signals from the I/O pin onto a plurality of internalsignal lines, the receiving circuit having a reset line and beingconfigured to receive configuration data through the I/O pin uponreceiving a signal on the reset line and to thereafter de-multiplexsignals from the I/O pin according to the configuration data.
 14. Theelectronic device of claim 13, wherein the semiconductor chip is a firstsemiconductor chip, the device further comprising a second semiconductorchip coupled to the I/O pin and the reset line and including atransmitter, the transmitter operable to transmit configuration datafrom the I/O pin upon receiving a signal on the reset line and tosubsequently send multiplexed signals from the I/O pin according to theconfiguration data.
 15. The electronic device of claim 13, wherein theconfiguration data is one or more signal line identifiers eachcorresponding to one of the plurality of signal lines.
 16. Theelectronic device of claim 13, wherein the transmitting circuit and thereceiving circuit are driven by a common clock signal coupled to boththe transmitting circuit and the receiving circuit.
 17. The electronicdevice of claim 13, wherein the reset signal is sent to the transmittingcircuit and the receiving circuit during a computer system boot upoperation.
 18. A method for multiplexing signals comprising: exerting areset signal on a semiconductor chip having a transmitter circuit and aninitialization circuit, the initialization circuit receiving the resetsignal and causing the transmitter to serially transmit configurationinformation on a single I/O pin; transmitting data signals to thetransmitter over a plurality of signal lines coupled to the transmitter;and the transmitter multiplexing the data signals from selected lines ofthe plurality of signal lines on the I/O pin, the selected lines beingidentified by the configuration information.
 19. The method of claim 18,wherein the semiconductor chip is a first semiconductor chip, the methodfurther comprising receiving the configuration data at a secondsemiconductor chip including a receiving circuit, the receiving circuitde-multiplexing the data signals according to the configuration data.20. The method of claim 18, further comprising waiting for a delayperiod after exerting the reset signal before causing the transmitter toserially transmit the configuration information.